In an advanced super dimension switch (ADS) mode array substrate, an active region and source/drain may be formed in one patterning process in order to simplify manufacturing process. In this case, a pixel electrode is arranged on the source/drain, that is, the pixel electrode “laps” over the drain.
As shown in FIG. 1, in general, a drain 41, as well as a source 42, has a relatively large thickness of about hundreds of microns, while a pixel electrode 5 has a relatively small thickness of tens of microns. Therefore, in the case that the edge of the drain 41 has a relatively large slope angle (90 degrees in the figure, for example), a part (lap portion 51) of the pixel electrode 5 which “laps” over the drain 41 is very likely to disconnect from a part (main body portion 52) of the pixel electrode 5 beyond the drain 41 at the edge of the drain 41 (i.e., at the joint between the lap portion 51 and the main body portion 52), thus affecting the function of the array substrate. Needless to say, the array substrate may further include therein other known structures such as a base 9, a gate 1, a gate insulation layer 2, an active region 3, a planarization layer 6, a common electrode 7, and the like, which are not described repeatedly here.